In a comparator circuit, two input voltages are compared and an output voltage representative of the difference between the input voltages is generated. The comparison is typically performed by way of a differential pair of transistors.
FIG. 1 shows an example of differential pairs of transistors, which pairs are configured to be incorporated into a comparator but have shortcomings in terms of efficiency.
The transistors of the differential pairs preferably have very close features, in particular the voltage threshold, in order to ensure accurate comparison. Due to manufacturing uncertainties with the transistors, it is difficult to manufacture paired transistors having strictly the same features for a reasonable cost. Typically, to pair the transistors of a differential pair, resistive compensators 20, including resistive elements 21, 23 that are connected to the sources of the transistors of the differential pair, make it possible to apply a corrective potential to the respective sources. The corrective potential pre-biases the gate-source voltages of the transistors of the pair so that they exhibit similar behavior in response to the input voltages IN−, IN+ on their gates. This improves the input accuracy of the comparator.
Moreover, hysteresis between the input voltages IN−, IN+ is generally introduced following triggering of a comparison. The hysteresis effect ensures that stray comparisons due to unforeseen variations, for example due to electrical noise, are avoided. The hysteresis effect is typically achieved by modifying the conductivity of one transistor of the differential pair, biasing the input value necessary to trigger the transistors. For example, to modify the conductivity of a transistor, one conventional solution involves connecting or disconnecting, upon request, a stack of transistors 11, 12, 13, 14, 15, 16, 17 in parallel to or from one of the transistors of a differential pair.
This type of hysteresis structure 10 requires a non-negligible surface area in order to be implemented, and the transistors in parallel 11-17 introduce a stray capacitance at input IN−, IN+, which increases the propagation delay of the signal in the comparator. For example, the stray capacitance, such as the gate capacitances of the transistors in parallel 11-17, may have a value of more than five times the input capacitance without a hysteresis structure 10.
Furthermore, the resistive elements 21, 23 belonging to the resistive compensators 20 typically introduce a stray polysilicon/substrate capacitance to the sources of the transistors of the differential pairs.
In comparators that are intended to be highly efficient, in particular in terms of input-output propagation speed, these stray capacitances are extremely detrimental and difficult to reduce in the art.
There is thus a need to design high-speed comparators whose input capacitance is minimized, while at the same time retaining the input accuracy and the generation of a hysteresis effect.